Integrated memory may be used in computer systems for storing data. Integrated memory is usually fabricated in one or more arrays of individual memory cells. The memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
An example memory cell is a programmable metallization cell (PMC). Such may be alternatively referred to as conductive bridging random access memory (CBRAM), nanobridge memory, or electrolyte memory. A PMC may use ion conductive switching material (for instance, a suitable chalcogenide or any of various suitable oxides) and an ion source material adjacent the switching material. The ion source material and switching material may be provided between a pair of electrodes. A suitable voltage applied across the electrodes can cause ions to migrate from the ion source material into the switching material to thereby create one or more current-conductive paths through the switching material. An opposite voltage applied across the electrodes essentially reverses the process and thus removes the current-conductive paths. A PMC thus comprises a high resistance state (corresponding to the state lacking a conductive bridge extending through a switching material) and a low resistance state (corresponding to the state having a conductive bridge extending through the switching material), with such states being reversibly interchangeable with one another.
Referring to FIG. 1, a prior art memory cell 200 is illustrated in two modes corresponding to a high resistance state (HRS) and a low resistance state (LRS). The two modes are reversibly interchanged with one another through application of electric fields EF(+) and EF(−), with EF(+) being of opposite polarity relative to EF(−).
The memory cell comprises a pair of electrodes 212 and 214. The memory cell also comprises a dielectric region 216 over the electrode 214, an ion buffer region 218 over the dielectric region, and an ion source region 220 between the ion buffer region and the electrode 212.
The memory cell 200 is shown to have the electrode 212 connected to external circuitry 230, and to have the electrode 214 connected to external circuitry 232. Circuitries 230 and 232 may include sense and/or access lines coupled to the electrodes, and configured for providing appropriate electric fields across the memory cell during read/write operations.
A conductive bridge 226 forms across regions 216 and 218 in transitioning from the HRS mode to the LRS mode. Although only one conductive bridge is shown, there may be multiple conductive bridges present in the LRS mode. Also, although the conductive bridge 226 is shown to span an entire distance from a top surface of electrode 214 to a bottom surface of ion source region 220, the conductive bridge may alternatively only extend partially across such distance. For instance, a conductive bridge may be discontinuous, and may be broken by one or more small gaps. In operation, charge carriers may “jump” such gaps to complete a circuit. Although the conductive bridge 226 is shown to be entirely absent in the HRS mode of the cell, in some applications a portion of the conductive bridge may be present in the HRS mode.
The ion source region 220 contributes ions which ultimately form the conductive bridge 226.
A difficulty which may be encountered in utilizing memory cells of the type described in FIG. 1 is that there may be excess ions available in transitioning to the LRS mode so that the ion concentration excessively builds up during formation of filament 226 (such may be referred to as an “overset” problem). The excess ions may eventually lead to cycling failure of the memory cells.
It is desired to develop improved memory cells.